I2C
Requirements
I2C is a protocol which allows one master chip (usually a micro controller) to communicate with multiple slaves (usually sensors or modems). It is a serial (two wire) synchronous protocol requiring a data (SDA) and a clock (SCL) line and supports up to 1008 concurrent devices.
The clock signal is generated by the master chip. Slaves can pull the clock low to delay the master from sending more data.
Messages are split into two types of frames: an address frame to decide which slave device is addressed, and one or more data frames.
Address frame
Start condition: the master pulls SDA low while SCL is high. This makes the slaves wait for a transmission. The address frame then contains the 7 bit address with the MSB first, followed by a bit indicating whether this is a read (1) or write (0) operation. The last bit of the frame is the NACK/ACK bit. After the first 8 bits of the frame, the slave gets control of the SDA line. If it pulls down SDA before the 9th clock pulse, the frame is considered ACKed, if not it is considered NACKed.
Data frame
For data transmission, the master continues generating clock pulses and either the master or the slave (depending on whether it was a read or write operation) send the data over the SDA line. Stop condition: once all the data has been sent, the controller will send the stop condition. This is done by pulling SDA high after SCL has gone high.
Reading data (usually)
- Write an address frame containing the device address and the R/W bit set to R
- Write a data frame containing the register address (register selection)
- Read the expected data
Writing data (usually)
- Write an address frame containing the device address and the R/W bit set to W
- Write a data frame containing the register address (register selection)
- Write one or more data frames containing the data to write
Terminology in datasheets
- The device addressing + r/w frame is usually called
SAD+R
orSAD+W
- The register addressing frame is usually called
SUB
- Data frames are usually called
DATA
Advantages
- Low number of lines
- Flexible amount of data
- Two way communication
- Multiple peripherials
Disadvantages
- Slow-ish (100kHz or 400kHz)
- 11% overhead (1 bit for 8 bit of data)