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I2C

Requirements

I2C is a protocol which allows one master chip (usually a micro controller) to communicate with multiple slaves (usually sensors or modems). It is a serial (two wire) synchronous protocol requiring a data (SDA) and a clock (SCL) line and supports up to 1008 concurrent devices.

The clock signal is generated by the master chip. Slaves can pull the clock low to delay the master from sending more data.

Messages are split into two types of frames: an address frame to decide which slave device is addressed, and one or more data frames.

Address frame

Start condition: the master pulls SDA low while SCL is high. This makes the slaves wait for a transmission. The address frame then contains the 7 bit address with the MSB first, followed by a bit indicating whether this is a read (1) or write (0) operation. The last bit of the frame is the NACK/ACK bit. After the first 8 bits of the frame, the slave gets control of the SDA line. If it pulls down SDA before the 9th clock pulse, the frame is considered ACKed, if not it is considered NACKed.

Data frame

For data transmission, the master continues generating clock pulses and either the master or the slave (depending on whether it was a read or write operation) send the data over the SDA line. Stop condition: once all the data has been sent, the controller will send the stop condition. This is done by pulling SDA high after SCL has gone high.

Reading data (usually)

Writing data (usually)

Terminology in datasheets

Advantages

Disadvantages